招聘职位

Design Engineer

 

Operating duty:

•    Develop RTL for IP blocks and participate in synthesis, timing closure
•    Collaborate closely with algorithm developers, architects, and SoC designers to define and support all phases of Silicon SoC development from definition, specification, architecture, layout and production
•    This position offers interactions with several ASIC development disciplines and will require communication and coordination with these teams, some members being in remote location

 

Recruitment requirements:

•    Bachelors or Master Degree with 1-5 years of experience in digital IC design, using Synopsys or Cadence IC design tools and high-speed simulation tools
•    Solid hardware engineering background with a concentration in VLSI and Computer Architecture 
•    Experience in Verilog or System Verilog. Fluent programming with Perl/Python (or similar scripting languages) and/or C/C++
•    Experience with logic synthesis and timing analysis. Additional experience working on embedded processors is desired but not required
•    Experience with techniques for power/area/performance optimizations
•    Design experience with High Performance Parallel Computing ASICs like GPU or Deep Learning IP is a big plus
•    Good debugging and analytical skills and mindset
•    Communication skills and demonstrated ability to cross multi-disciplinary boundaries
•    Experience working as an individual and in a multidisciplinary international team

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