招聘职位

Verification Engineer

Operating duty:

•    Develop test benches for verifying ASIC design
•    Work closely with ASIC designer and design verification engineers to verify ASIC design
•    Develop verification environment in SystemC/System Verilog for verifying multi-core designs
•    Develop bus functional models, drivers, monitors and sequencers
•    Prepare test plan and write constrained-random tests by fully understanding the design specification
•    Analyze coverage results and identify verification holes

 

Recruitment requirements:

•    Bachelors or Master’s Degree with 1-5 years of experience in ASIC verification
•    Work experience in IP/SOC level verification
•    Proficient knowledge on System Verilog, UVM/OVM
•    Experience with constrained-random, coverage driven verification environments
•    Strong skills at C/C++/System C Perl/Python scripting
•    Knowledge in multi-core, CPU, GPU, SIMD is a plus

 

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